AT89C5122D-RDRUM datasheet(142/208 Pages) ATMEL

142 / 208 page

142

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = 00010100b

Table 85.

Serial Peripheral Control Register - SPCON (C3h)

7654

3210

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

Number

Bit

Mnemonic

R/W

Mode

Description

7SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate

SPEN

Serial Peripheral Enable

Clear to disable the SPI interface (internal reset of the SPI)

Set to enable the SPI interface

5SSDIS

SS Disable

Clear to enable SS in both Master and Slave modes

Set to disable SS in both Master and Slave modes. In Slave mode, this

bit has no effect if CPHA = ’0’

4MSTR

Serial Peripheral Master

Clear to configure the SPI as a Slave

Set to configure the SPI as a Master

3CPOL

Clock Polarity

Clear to have the SCK set to ’0’ in idle state

Set to have the SCK set to ’1’ in idle low

2CPHA

Clock Phase

Clear to have the data sampled when the SPSCK leaves the idle state

(see CPOL)

Set to have the data sampled when the SPSCK returns to idle state

(see CPOL)

1SPR1

Serial Peripheral Rate

(SPR2:SPR1:SPR0)

000: Reserved

001: FCK_SPI /4

010: FCK_SPI/8

011: FCK_SPI/16

0SPR0

100: FCK_SPI/32

101: FCK_SPI/64

110: FCK_SPI/128

111: Reserved

AT89C5122D-RDRUM 数据表(PDF) 142 Page - ATMEL Corporation

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