EM357-RTR datasheet(134/240 Pages) ETC2

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EM351 / EM357

If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture flag INT_TIMMISSCCyIF

in the INT_TIMxMISS register is set. INT_TIMCCyIF can be cleared by software writing a 1 to its bit or reading

the captured data stored in the TIMx_CCRy register. To clear the INT_TIMMISSCCyIF bit, write a 1 to it.

The following example shows how to capture the counter value in the TIMx_CCR1 when the TI1 input rises.

Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the TIM_CC1S bits to 01 in the

TIMx_CCMR1 register. As soon as TIM_CC1S becomes different from 00, the channel is configured in input

and the TIMx_CCR1 register becomes read-only.

Program the required input filter duration with respect to the signal connected to the timer, when the

input is one of the TIy (ICyF bits in the TIMx_CCMR1 register). Consider a situation in which, when toggling,

the input signal is unstable during at most 5 internal clock cycles. The filter duration must be longer than

these 5 clock cycles. The transition on TI1 can be validated when 8 consecutive samples with the new level

have been detected (sampled at PCLK frequency). To do this, write the TIM_IC1F bits to 0011 in the

TIMx_CCMR1 register.

Select the edge of the active transition on the TI1 channel: Write the TIM_CC1P bit to 0 in the TIMx_CCER

Program the input prescaler: In this example, the capture is to be performed at each valid transition, so

the prescaler is disabled (write the TIM_IC1PS bits to 00 in the TIMx_CCMR1 register).

Enable capture from the counter into the capture register: Set the TIM_CC1E bit in the TIMx_CCER

If needed, enable the related interrupt request by setting the INT_TIMCC1IF bit in the INT_TIMxCFG

When an input capture occurs:

• The TIMx_CCR1 register gets the value of the counter on the active transition.

• INT_TIMCC1IF flag is set (capture/compare interrupt flag). The missed capture/compare flag

INT_TIMMISSCC1IF in INT_TIMxMISS is also set if another capture occurs before the INT_TIMCC1IF

flag is cleared.

• An interrupt may be generated if enabled by the INT_TIMCC1IF bit.

To detect missed captures reliably, read captured data in TIMxCCRy before checking the missed

capture/compare flag. This sequence avoids missing a capture that could happen after reading the flag and

before reading the data.

Note:

Software can generate IC interrupt requests by setting the corresponding TIM_CCyG bit in the TIMx_EGR

9.3.6

PWM Input Mode

This mode is a particular case of input capture mode. The procedure is the same except:

Two ICy signals are mapped on the same TIy input.

These two ICy signals are active on edges with opposite polarity.

One of the two TIyFP signals is selected as trigger input and the slave mode controller is configured in

reset mode.

For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the TIMx_CCR2 register of

the PWM applied on TI1, use the following procedure depending on CK_INT frequency and prescaler value:

Select the active input for TIMx_CCR1: write the TIM_CC1S bits to 01 in the TIMx_CCMR1 register (TI1

selected).

Select the active polarity for TI1FP1, used both for capture in the TIMx_CCR1 and counter clear, by writing

the TIM_CC1P bit to 0 (active on rising edge).

9-14

120-035X-000D

Preliminary

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