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EM357-RTR 数据表(PDF) 184 Page - List of Unclassifed Manufacturers

部件名 EM357-RTR
功能描述  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  240 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC2 [List of Unclassifed Manufacturers]
网页  
标志 ETC2 - List of Unclassifed Manufacturers

EM357-RTR 数据表(HTML) 184 Page - List of Unclassifed Manufacturers

Back Button EM357-RTR Datasheet HTML 180Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 181Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 182Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 183Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 184Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 185Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 186Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 187Page - List of Unclassifed Manufacturers EM357-RTR Datasheet HTML 188Page - List of Unclassifed Manufacturers Next Button
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EM351 / EM357
SNR (dB)
Single-Ended
Differential
35
35
44
44
53
53
62
62
70
71
75
77
77
79
77
80
SINAD (dB)
Single-Ended
Differential
35
35
44
44
53
53
61
62
67
70
69
75
70
76
70
76
SDFR (dB)
Single-Ended
Differential
59
60
68
69
72
77
72
80
72
81
72
81
72
81
73
81
THD (dB)
Single-Ended
Differential
-45
-45
-54
-54
-62
-63
-67
-71
-69
-75
-69
-76
-69
-76
-69
-76
ENOB (from SNR)
Single-Ended
Differential
5.6
5.6
7.1
7.1
8.6
8.6
10.0
10.1
11.3
11.4
12.2
12.5
12.4
12.9
12.5
12.9
ENOB (from SINAD)
Single-Ended
Differential
5.5
5.6
7.0
7.0
8.5
8.5
9.9
10.0
10.9
11.3
11.2
12.1
11.3
12.3
11.3
12.4
Equivalent ADC Bits
7
[15:9]
8
[15:8]
9
[15:7]
10
[15:6]
11
[15:5]
12
[15:4]
13
[15:3]
14
[15:2]
Note:
INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of Table 10-6.
ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or
SINAD (signal-to-noise and distortion ratio).
Table 10-7 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling rate of
6 MHz. ADC_HVSELP and ADC_HVSELN are programmed to 0 to disable the input buffer. The single-ended
measurements were done at finput = 7.7% fNyquist; 0 dBFS level (where full-scale is a 1.2 V p-p swing). The
differential measurements were done at finput = 7.7% fNyquist; -6 dBFS level (where full-scale is a 2.4 V p-p
swing) and a common mode voltage of 0.6V
Table 10-7. ADC Module Key Parameters for 6 MHz sampling
Parameter
Performance
ADC_PERIOD
0
1
2
3
4
5
6
7
Conversion Time (µs)
5.33
10.7
21.3
42.7
85.3
171
341
683
Nyquist Freq (kHz)
93.8k
46.9k
23.4k
11.7k
5.86k
2.93k
1.47k
732
3 dB Cut-off (kHz)
56.6k
28.3k
14.1k
7.07k
3.54k
1.77k
884
442
INL (codes peak)
0.084
0.084
0.15
0.274
0.518
1.057
2.106
4.174
INL (codes RMS)
0.046
0.044
0.076
0.147
0.292
0.58
1.14
2.352
DNL (codes peak)
0.026
0.023
0.044
0.052
0.096
0.119
0.196
0.371
10-9
120-035X-000D
Preliminary



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