EM357-RTR datasheet(182/240 Pages) ETC2

182 / 240 page

EM351 / EM357

1. Allocate a 16-bit signed variable, for example analogData, to receive the ADC output.

(Make sure that analogData is half-word aligned – that is, at an even address.)

2. Disable all ADC interrupts: Write 0 to the INT_ADCCFG register.

3. Set up the DMA to output conversion results to the variable, analogData.

Reset the DMA: Set the ADC_DMARST bit in ADC_DMACFG register.

Define a one sample buffer: Write analogData’s address to the ADC_DMABEG register and set the

ADC_DMASIZE register to 1.

4. Write the desired offset and gain correction values to the ADC_OFFSET and ADC_GAIN registers.

5. Start the ADC and the DMA.

Write the desired conversion configuration, with the ADC_EN bit set, to the ADC_CFG register.

Clear the ADC buffer full flag: Write the INT_ADCULDFULL bit to the INT_ADCFLAG register.

Start the DMA in auto wrap mode: Set the ADC_DMAAUTOWRAP and ADC_DMALOAD bits in the

ADC_DMACFG register.

6. Wait until the INT_ADCULDFULL bit is set in the INT_ADCFLAG register, then read the result from

analogData.

To convert multiple inputs using this approach, repeat steps 4 through 6, loading the desired input

configurations to the ADC_CFG register in step 5. If the inputs can use the same offset/gain correction, just

repeat steps 5 and 6.

10.4

Calibration

Sampling of internal connections GND, VREF/2, and VREF allow for offset and gain calibration of the ADC in

applications where absolute accuracy is important. Offset error is calculated from the minimum input and gain

error is calculated from the full scale input range. Correction using VREF is recommended because VREF is

calibrated by the Ember software against VDD_PADSA. The VDD_PADSA regulator is factory-trimmed to 1.80 V

± 20 mV. If better absolute accuracy is required, the ADC can be configured to use an external reference. The

ADC calibrates as a single-ended measurement. Differential signals require correction of both their inputs.

Table 10-5 shows the equations used to calculate the gain and offset correction values

Table 10-5. ADC Gain and offset correction equations

Calibration

Correction value

Gain, buffer disabled

4000

)

(

8000

GND

VREF −

Gain, buffer enabled

2000

)

(

8000

−

VREF

Offset, buffer disabled

( after applying gain correction )

)

000

(

GND −

Offset, buffer enabled

( after applying gain correction )

)

800

(

VREF

−

Equation notes

All N are 16-bit two’s complement numbers.

NGND is a sampling of ground. Due to the ADC's internal design, VGND does not yield the minimum two’s

complement value 0x8000 as the conversion result. Instead, VGND yields a two’s complement value close

to 0xE000 when the input buffer is not selected. VGND cannot be measured when the input buffer is

enabled because it is outside the buffer’s input range.

10-7

120-035X-000D

Preliminary

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