FS401LF datasheet(22/104 Pages) ETC2

22 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

In the HCRS register:

LNTCH

Luminance Notch Filter

CBP

Chroma Bandpass Filter

PEDSTL

US NTSC Black Pedestal

In the HCRES register:

RGBGAIN

1x or 1.43x RGB Input Gain

FREEZE

Freeze the Input Image

In the SCR register

SFLK

Flicker Filter

4.2.6 Video Mode Changes

A video mode change starts when the internal micro-controller detects a significant change in either IVC

(Input Vertical Count) or IHC (Input Horizontal Count). The internal micro-controller samples IVC and IHC

approximately every 50ms. When a change is detected and is stable for several sample periods, the

mode change process is started and the MCS (Mode Change Start) bit is set in the SSR register.

Additionally, a mode change is initiated when the RSTVMODE bit is set in the SCR register or when the

OCAL bit in the SCR register is cleared.

If the input calibration tables are enabled (ENICTBL bit in the SCR register is set), then the accumulated

input calibration for the old video mode is stored in the input calibration table. Next, the input calibration

table is searched for an entry that matches the IVC and IHC of the new mode. If one is found, then the

input calibration is retrieved from the table.

If manual input calibration is enabled (DSICAL bit in SCR register is set) and the no input calibration

information was found in the input calibration table, then the input calibration information is retrieved from

the manual input calibration configuration values.

If auto input calibration is enabled (DSICAL bit in SCR register is clear) and the no input calibration

information was found in the input calibration table, then the internal micro-controller begins sampling of

the active video registers (SHV, EHV, SVV, and EVV).

Once the input calibration information is obtained, the internal micro-controller calculates the values for

the low-level hardware registers and programs them. At this point the MCS bit in the SSR is cleared and

the MCC (Mode Change Complete) bit in the SSR is set.

A video mode change does not change the state of any other software registers. This includes the

FREEZE and ZOOM bits in the HCRES register and the HPO, VPO, HPP, VPP, HSS, and VSS registers.

If the external controller modifies any of these, it might be desirable for the external controller to return

them to there reset state after a video mode change is complete.

An external controller can detect a video mode change by polling the MCC bit in the SSR. The MCC bit

remains set until an external controller sets the CLRMCC bit in the SCR register. The recommended

polling frequency is at least once per second, but not more than 20 times per second.

4.2.7 By-passing the Internal Micro-Controller

When the FS400’s built-in microprocessor is enabled, it is responsible for programming the following low-

level hardware registers:

IHO

Input Horizontal Offset

IVO

Input Vertical Offset

FS401LF 数据表(PDF) 22 Page - List of Unclassifed Manufacturers

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