FS401LF datasheet(80/104 Pages) ETC2

80 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

0.1

0.2

0.3

0.4

0.5

Horizontal

14 Degrees

27 Degrees

45 Degrees

Normalized Vertical Frequency

Figure 10: FLK = 16, SHP = 16; Response at Horizontal, 14, 27, 45 Degrees

5.2 Frame Store Controller

The Frame Store Controller (FSC) coordinates pixel data transfer between the FS400 and the Frame

buffer. For normal operation, a 16 Mbit SDRAM is connected to the frame store controller port.

Supported SDRAM parts include:

NEC

µPD451616G5-A10

NEC

µPD4516161AG5-A10B

Samsung

KM416S1120A-G/F10

Samsung

KM416S1020CT-F10

GM72V161621CT-10

MOSEL VITALIC

V-54C316162T-10

Hyundai

HY57V161610BTC-10

The refresh of data in the SDRAM is accomplished through the continual update of the video output

display. Therefore, any SDRAM selected must meet the frame rate maximum delay of the selected

video. The worst case delay time is for PAL systems (25 frames/s) requiring a retention time of 40ms or

greater.

Data from the Capture Engine is written into the frame store in parallel with the extraction of data for the

encoder engine. Read and write buffers at the data port allow data to be transferred in bursts without

interruption of the overall flow of pixels. Bandwidth of the FSC bus is 80 MHz or 100 MHz, sufficient to

support maximum rate write cycles from the Capture Engine simultaneously with full rate Encoder Engine

read cycles.

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