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FS401LF 数据表(PDF) 93 Page - List of Unclassifed Manufacturers

部件名 FS401LF
功能描述  PC to TV Video Scan Converters
PDF  104 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

FS401LF 数据表(HTML) 93 Page - List of Unclassifed Manufacturers

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FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
93
JANUARY 24, 2007
COPYRIGHT
© 1999 FOCUS ENHANCEMENTS, INC.
6.4 Switching Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
Clocks
fCKIN_N NTSC Reference Clock Frequency
14.31818
MHz
fCKIN_P PAL Reference Clock Frequency
17.734475
MHz
fXTOL
Reference Clock Frequency Tolerance
50
50
2
ppm
tPWH
Reference Clock Pulse Width, HIGH
40
ns
tPWL
Reference Clock Pulse Width, LOW
40
ns
Reset
Assert time on RESET to reset the part
8
Clocks
Incoming Syncs
fH
HS_IN frequency
24
100
KHz
fV
VS_IN frequency
50
130
Hz
NH
Number of lines per frame
100
4095
tPWHS
HS_IN Pulsewidth
1
µs
tVS-HS
VS_IN to HS_IN Delay
0
ns
tDS
Sync Delay (VGA Sync to Sync Out)
100
ns
Video Output
tDOV
Analog Output Delay (4fSC clock to Video Out)
30
ns
tR
D/A Output Current Risetime (10% to 90%)
10
ns
tF
D/A Output Current Falltime (90% to 10%)
10
ns
SKEW
D/A to D/A Skew
-3
0
3
ns
SDRAM Frame Buffer Interface
tFCKL
FS_CK pulse width, LOW
5.0
ns
tFCKH
FS_CK pulse width, HIGH
5.0
ns
tFSCO
FS_CK to RAS\, CAS\, WE\ DQM\ out delay
2.0
ns
tFDSU
FS_CK to data setup time
3.0
ns
tFDHO
FS_CK to data hold time
3.0
ns
tFDO
FS_CK to data out delay
2.0
ns
tFAO
FS_CK to address out delay
2.0
ns
Serial Microprocessor Interface
tDAL
SIOCLK Pulse Width, LOW
1.3
µs
tDAH
SIOCLK Pulse Width, HIGH
0.6
µs
tSTAH
SIODATA Start Hold Time
0.6
µs
tSTASU SIOCLK to SIODATA Setup Time (Stop)
0.6
µs
tSTOSU SIOCLK to SIODATA Setup Time (Start)
0.6
µs
tBUFF
SIODATA Stop Hold Time Setup
1.3
µs
tDSU
SIODATA to SIOCLK Data Setup Time
300
ns
tDHO
SIODATA to SIOCLK Data Hold Time
300
ns
Notes:
1. Values shown in Typ column are typical for VDD = VDDA = +3.3V and TA = 25°C
2. TV subcarrier acceptance band is
± 300 Hz.



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