FS401LF datasheet(76/104 Pages) ETC2

76 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

IHC (read only)

EHV (read only)

AVT

IVC (read only)

SVV (read only)

Capture Control also coordinates hand off of data to the Frame Store Controller.

Input Horizontal Samples, IHS is the 11-bit terminal count of the number of pixels per horizontal line

between sync pulses. IHS is the value programmed into the ADCK phase-locked-loop. If, for example

there are to be 800 samples per incoming line, then IHS must be programmed to be 799.

Input Horizontal Count, IHC is the number of encoder clock pulses on the selected OSC clock that occur

between horizontal sync pulses. This count is stored in the IHC register that can be read via the serial

bus for automatic detection of the format of incoming video.

Input Vertical Count, IVC is the 12-bit terminal count of the number of lines that occur between the

vertical sync pulses. This count is stored in the IVC register that can be read via the serial bus for

automatic detection of the format of incoming video.

Start Horizontal Active VGA, SHV is the number of ADC clock pulses that occur from the start of the

horizontal sync pulse to the detection of incoming active video. This is used to permit an accurate

positioning of the incoming VGA on the TV.

End Horizontal Active VGA, EHV is the number of ADC clock pulses that occur from the start of the

horizontal sync pulse to the end of detected incoming active video. This is used to permit an accurate

positioning of the incoming VGA on the TV.

Start Vertical Active VGA, SVV is the number of lines that occur from the start of the vertical sync pulse to

the detection of incoming active video. This is used to permit an accurate positioning of the incoming

VGA on the TV.

End Vertical Active VGA, EVV is the number of lines that occur from the start of the vertical sync pulse to

the end of detected incoming active video. This is used to permit an accurate positioning of the incoming

VGA on the TV.

5.1.2 Clamps

Incoming RGB video signals must be AC coupled to the A/D converters. Preceding each A/D converter is

an FET clamp switch which establishes the black reference level of each video signal by shorting the A/D

converter input to ground when the clamp signal is active. Clamp timing is derived internally from the

HS_IN input. A digital output, CLAMP_REF = H, when the clamp is active. CLAMP_REF and

VGACLKDIV polarity are set by the VGAREFPOL bit in the CRE register.

5.1.3 Analog-to-Digital Converters

Bottom reference voltage of the A/D converters is ground. Top reference voltage, VT is a high impedance

input that is applied via voltage followers to the reference ladder network of each A/D converter. VT must

be de-coupled with a 0.1µF capacitor to ground.

VT can be derived from the internal reference voltage, VREF by splitting the resistor connected to IREF as

described in the 5.3.5 Digital-to-Analog Converters section.

To avoid aliasing effects, incoming RGB video signals should be filtered by a low pass filter prior to the

AC coupling capacitor. Filter cutout frequency should be set at half the highest expected sampling rate of

the A/D converter clock, ADCK. A simple two element RC filter is adequate. 20MHz is typically used as

a cut off frequency.

Phase of ADCK is set by the Command Register Extended VGACLKPOL bit. By flipping the phase of the

sampling clock by 180

°, the sampling points can be positioned closer to the center of incoming pixels.

Figure 6 shows optimum sampling of VGA pixels on the rising edge of the ADCLK signal, when

synchronous sampling is chosen.

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