FS401LF datasheet(96/104 Pages) ETC2

96 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

7.2 FS400 Design and Layout Considerations

Careful circuit design and layout are key factors that insure a successful implementation of the FS400 in

a product. The following guidelines will help insure that your design yields the best possible results.

7.2.1 Video Input to A-D Converters

• Consider using a higher capacitor value and a lower resistor value in the input filter. For example, use

100

Ω and 100pF instead of 220Ω and 47pF. This will reduce noise at the ADC input.

• Place the input lowpass filter shunt capacitor as close as possible to the input pin on the FS400. This

capacitor acts as a reservoir of charge for the ADC’s input sampling circuitry, and limits the voltage

kickback from the sampling process.

• Make the video input traces to the A-D converters as short as possible. Do not route other signal

traces (especially clocks!) parallel to these traces, or close to the ADC inputs of the FS400. External

interference coupled into the video can easily be discerned by the eye at very low levels.

• Consider adding diodes to VDDAD and VSSAD on these lines to reduce the risk of ESD damage to the

FS400.

7.2.2 Input ADC Phase Lock Loop

• The analog supply for the ADC PLL should always be clean and noise free to insure minimum jitter in

the PLL. This applies regardless of the PLL used, internal or external. Do not power other circuitry

from the PLL supply.

• When using the internal PLL, the supply line VDDPA should be decoupled with a series resistor of 150Ω

and a 4.7

µF tantalum capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100µF. Always

have a 1000pF to 0.1

µF capacitor to remove high frequency noise.

• Do not run other traces (especially clocks) near an external PLL.

• Use a solid ground plane under the FS400.

7.2.3 Memory Clock Phase Lock Loop

• When using an external PLL for the memory clock, series terminate the clock line, and keep the traces

as short as possible to reduce EMI.

• Avoid using an even multiple of the 4fSC clock as your memory clock. This increases EMI since

multiples of the clocks that overlap are additive.

7.2.4 External SDRAM Interface

• Keep the traces from the FS400 to the external SDRAM as short as possible. Series terminate the

RAS\, CAS\, and FSCK_OUT as close as possible to the FS400. Consider series terminating the

address lines as well for further EMI reduction.

• Keep other traces, especially analog traces, away from the traces associated with the SDRAM. In

addition to 0.1

µF bypass capacitors, consider adding 100 to 1000pF capacitors to reduce higher

frequency noise on the power supply.

7.2.5 HSYNC and VSYNC

• The HSYNC and VSYNC inputs to the FS400 should be low pass filtered. 150

Ω and 100pF work well.

Consider termination on these lines if the input cable length gives rise to significant reflections,

undershoot and overshoot.

• Consider adding diodes to VDD and VSS on these lines to reduce the risk of ESD damage to the FS400.

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