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FS401LF 数据表(PDF) 81 Page - List of Unclassifed Manufacturers

部件名 FS401LF
功能描述  PC to TV Video Scan Converters
PDF  104 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

FS401LF 数据表(HTML) 81 Page - List of Unclassifed Manufacturers

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FS401, FS403
PRODUCT SPECIFICATION
REV. NO. 1.7
81
JANUARY 24, 2007
COPYRIGHT
© 1999 FOCUS ENHANCEMENTS, INC.
5.2.1 SDRAM Interface
The SDRAM Interface is designed to use a wide variety of 1Mx16 SDRAM parts. The critical parameters
to use in selecting an SDRAM are listed below:
<To be supplied later>
Figure 11. Timing Parameter Definition, SDRAM Interface
5.2.2 Phase Locked Loop
All SDRAM access is synchronized to the selected 4fSC clock derived from the OSC1 clock input. The
4fSC clock is divided by two, then depending upon the outgoing video standard selection, either NTSC or
PAL, multiplied x9, x11, or x14 by the Frame Store Controller Phase Locked Loop to create the 80 or 100
MHz SDRAM clock.
5.2.3 Input Offset and Size Control
Besides synchronizing all SDRAM access activities, the frame store controller also coordinates several
offset and size functions. These values are programmed into internal registers that control the setup of
the Frame Store Controller.
Input Horizontal Offset, IHO is an eleven bit value that sets the horizontal displacement of the captured
active video relative to the horizontal sync as show in Figure 12.
tFSSU
tFSHO
tFSCO
tFSAO
tFSDO
CLK
CS\
RAS\
CAS\
WE\
DQM\
A[11:0]
D[15:0]



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