FS401LF datasheet(24/104 Pages) ETC2

24 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

It is also possible to disable two portions of the internal micro-controllers program code. These are the

video mode detect and the auto input calibration program code.

The video mode detect program code is disabled by setting the DSVMDET bit in the SCR register. The

video mode detect code usually samples the IHC and IVC registers looking for a stable change to

indicate a new video mode. When this code is disabled, no new video modes will be detected. An

external processor could sample IHC and IVC or use another method to determine a video mode change.

The external processor would then have to program the CCR_IHC and the CCR_IVC configuration

values via the CCR and CDR and then set the RSTVMODE bit in the SCR to force a video mode update.

The video mode detect code can be re-enabled at any time by clearing the DSVMET bit in the SCR

Setting the DSICAL bit in the SCR register disables the input calibration program code. This referred to

as manual input calibration mode and is discussed in section 4.2.1.2 above.

4.2.8 Special Internal Micro-Controller SIO Requirements

The interface to the internal micro-controller’s software registers is identical to the hardware registers via

the SIO. However, the internal micro-controller is not able to process code while an external processor is

accessing the SIO. Therefore, repeated back to back SIO access can starve the internal micro-controller

of processing time. This is not a concern for short bursts of back to back SIO accesses, but long loops of

repeated polling of an SIO register should be avoided.

If it is necessary to repeatedly poll a register via the SIO, it is recommended that there be a delay of about

1 to 5 millisecond between SIO accesses. This will allow the internal micro-controller to continue it’s

processing in a timely manor.

One example of the need to repeated poll an SIO register is when an external processor writes a

CCR_READ command to the CCR register. The external processor must wait until the CCR register is

set to CCR_COMPLETE (0) before it could read the data from the CDR. A programmer might be

tempted to write a loop that continuously reads the CCR register until it is set to CCR_COMPLETE. This

would slow down or even stop the processing in the internal micro-controller. To avoid this, add at least a

1 to 5ms delay into the loop to allow the internal micro-controller to continue processing.

4.3 Disabling the Internal Micro-Controller

To be added later.

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