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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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910GL 数据表(PDF) 67 Page - Intel Corporation |
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910GL 数据表(HTML) 67 Page - Intel Corporation |
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67 / 426 page  Host Bridge/DRAM Controller Registers (D0:F0) R Datasheet 67 Address Offset Register Symbol Register Name Default Value Access 10E–10F C0BNKARC Channel A DRAM Bank Architecture 0000h R/W 110–113h — Reserved — — 114–117h C0DRT1 Channel A DRAM Timing Register 900122h R/W 118–11Fh — Reserved — — 120–123h C0DRC0 Channel A DRAM Controller Mode 0 00000000h R/W, RO 124–17Fh — Reserved — — 180h C1DRB0 Channel B DRAM Rank Boundary Address 0 00h R/W 181h C1DRB1 Channel B DRAM Rank Boundary Address 1 00h R/W 182h C1DRB2 Channel B DRAM Rank Boundary Address 2 00h R/W 183h C1DRB3 Channel B DRAM Rank Boundary Address 3 00h R/W 184–187h — Reserved — — 188h C1DRA0 Channel B DRAM Rank 0,1 Attribute 00h R/W 189h C1DRA2 Channel B DRAM Rank 2,3 Attribute 00h R/W 18A–18Bh — Reserved — — 18Ch C1DCLKDIS Channel B DRAM Clock Disable 00h R/W 18Dh — Reserved — — 18E–18Fh C1BNKARC Channel B Bank Architecture 0000h R/W 190–193h — Reserved — — 194h C1DRT1 Channel B DRAM Timing Register 1 900122h R/W, RO 195–19Fh — Reserved — — 1A0–1A3h C1DRC0 Channel B DRAM Controller Mode 0 00000000h R/W, RO 1A4–F0Fh — Reserved — — F10–F13h PMCFG Power Management Configuration 00000000h R/W F14h PMSTS Power Management Status 00000000h R/W/C/S |
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