 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
910GL 数据表(PDF) 72 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
910GL 数据表(HTML) 72 Page - Intel Corporation |
|
|
72 / 426 page  Host Bridge/DRAM Controller Registers (D0:F0) R 72 Datasheet 4.1.7 MLT—Master Latency Timer (D0:F0) PCI Device: 0 Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not implemented. Bit Access & Default Description 7:0 Reserved 4.1.8 HDR—Header Type (D0:F0) PCI Device: 0 Address Offset: 0Eh Default Value: 00h Access: RO Size: 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Access & Default Description 7:0 RO 00h PCI Header (HDR): This field always returns 0 to indicate that the (G)MCH is a single function device with standard header layout. 4.1.9 SVID—Subsystem Vendor Identification (D0:F0) PCI Device: 0 Address Offset: 2Ch Default Value: 0000h Access: R/WO Size: 16 bits This value is used to identify the vendor of the subsystem. Bit Access & Default Description 15:0 R/WO 0000h Subsystem Vendor ID (SUBVID): This field should be programmed during boot- up to indicate the vendor of the system board. After it has been written once, it becomes read only. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
