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910GL 数据表(PDF) 29 Page - Intel Corporation

部件名 910GL
功能描述  Express Chipset
PDF  426 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

910GL 数据表(HTML) 29 Page - Intel Corporation

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Introduction
R
Datasheet
29
Features of the PCI Express Interface include:
• One x16 PCI Express port intended for graphics attach, compatible with the PCI Express
Base Specification revision 1.0a.
• Theoretical PCI Express transfer rate of 2.5 Gb/s.
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a theoretical bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when (1)x16.
• PCI Express Graphics Extended Configuration Space. The first 256 bytes of configuration
space alias directly to the PCI Compatibility configuration space. The remaining portion of
the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as
extended configuration space.
• PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in
a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-relaxed
ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal
PCI 2.3 Configuration space as a PCI-to-PCI bridge)
• Supports “static” lane numbering reversal. This method of lane reversal is controlled by a
Hardware Reset strap, and reverses both the receivers and transmitters for all lanes (e.g.,
TX15->TX0, RX15->RX0). This method is transparent to all external devices and is different
than lane reversal as defined in the PCI Express Specification. In particular, link initialization
is not affected by static lane reversal.
1.3.5
Integrated Graphics (Intel
®
82915G/82915GV/82910GL/82915GL GMCH Only)
The 82915G/82915GV/82910GL/915GL GMCH provides an integrated graphics device (IGD)
delivering cost competitive 3D, 2D and video capabilities. The GMCH contains an extensive set
of instructions for 3D operations, BLT and Stretch BLT operations, motion compensation,
overlay, and display control. The GMCH’s video engines support video conferencing and other
video applications. The GMCH does not support a dedicated local graphics memory interface, it
may only be used in a UMA configuration. The GMCH also has the capability to support external
graphics accelerators via the PCI Express Graphics port but cannot work concurrently with the
integrated graphics devce. High bandwidth access to data is provided through the system memory
port. The GMCH also provides 3D hardware acceleration for block level transfers of data (BLTs).
2D BLTs are considered a special case of 3D transfers and use the 3D acceleration. The BLT
engine provides the ability to copy a source block of data to a destination and perform raster
operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination.
Performing these common tasks in hardware reduces processor load, and thus improves
performance.



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