910GL datasheet(28/426 Pages) INTEL

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Introduction

Datasheet

By using 256-Mb technology, the smallest memory capacity possible is 128 MB, assuming single-

channel mode. (16M rows * 16b/(row*device) * 4 devices/DIMM-side * 1 DIMM-side/channel *

1 channel *1B/8b = 128 MB). By using 1-Gb technology in dual-channel interleaved mode, the

largest memory capacity possible is 8 GB. (128M rows * 8b/(row*device) * 8 devices/DIMM-

side * 4 DIMM-sides/channel * 2 channels * 1B/8b * 1G/1024M = 8 GB). This exceeds a 32-bit

address limit of 4 GB. In a 32-bit system, only the first 4 GB of memory will be accessible.

The (G)MCH supports a memory thermal management scheme to selectively manage reads and/or

writes. Memory thermal management can be triggered either by on-die thermal sensor, or by

preset limits. Management limits are determined by weighted sum of various commands that are

scheduled on the memory interface.

1.3.3

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and ICH6.

This high-speed interface integrates advanced priority-based servicing allowing for concurrent

traffic and true isochronous transfer capabilities. Base functionality is completely software

transparent permitting current and legacy software to operate normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions,

the ICH6 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a

fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of

traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both

ends of the DMI link (i.e., the ICH6 and (G)MCH). Features of the DMI include:

• A chip-to-chip connection interface to ICH6

• 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction)

• 100 MHz reference clock (shared with PCI Express Graphics Attach).

• 32-bit downstream addressing

• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt”

broadcast message when initiated by the processor.

• Message Signaled Interrupt (MSI) messages

• SMI, SCI and SERR error indication

• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

DMA, floppy drive, and LPC bus masters

1.3.4

PCI Express* Graphics Interface (Intel

® 82915G/82915P/

and 82915PL Only)

The (G)MCH (82915G, 82915P, and 82915PL only) contains a 16-lane (x16) PCI Express port

intended for an external PCI Express graphics card. The PCI Express port is compatible with the

PCI Express Base Specification revision 1.0a. The x16 port operates at a frequency of 2.5 Gb/s on

each lane while employing 8b/10b encoding, and supports a maximum theoretical bandwidth of

4 Gb/s each direction. The 82915G GMCH multiplexes the PCI Express interface with two Intel

SDVO ports.

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