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3.4

I/O Mapped Registers

The (G)MCH contains two registers that reside in the processor I/O address space

− the

Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data

(CONFIG_DATA) Register. The Configuration Address Register enables/disables the

configuration space and determines what portion of configuration space is visible through the

Configuration Data window.

3.4.1

CONFIG_ADDRESS—Configuration Address Register

I/O Address:

0CF8h Accessed as a DWord

Default Value:

00000000h

Access:

R/W

Size:

32 bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or Word

reference will "pass through" the Configuration Address Register and DMI onto the Primary PCI

bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device

Number, Function Number, and Register Number for which a subsequent configuration access is

intended.

Bit

Access

Default

Description

R/W

Configuration Enable (CFGE):

1 = Enable

0 = Disable

30:24

Reserved

23:16

R/W

00h

Bus Number: If the Bus Number is programmed to 00h the target of the

Configuration Cycle is a PCI Bus #0 agent. If this is the case and the (G)MCH is

not the target (i.e., the device number is

≥ 3 and not equal to 7), then a DMI Type

0 Configuration Cycle is generated.

If the Bus Number is non-zero, and does not fall within the ranges enumerated by

device 1’s Secondary Bus Number or Subordinate Bus Number Register, then a

DMI Type 1 Configuration Cycle is generated.

If the Bus Number is non-zero and matches the value programmed into the

Secondary Bus Number Register of device 1, a Type 0 PCI configuration cycle will

be generated on PCI Express Graphics.

If the Bus Number is non-zero, greater than the value in the Secondary Bus

Number register of device 1 and less than or equal to the value programmed into

the Subordinate Bus Number Register of device 1 a Type 1 PCI configuration

cycle will be generated on PCI Express Graphics.

This field is mapped to byte 8 [7:0] of the request header format during PCI

Express Configuration cycles and A[23:16] during the DMI Type 1 configuration

cycles.

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