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910GL 数据表(PDF) 47 Page - Intel Corporation

部件名 910GL
功能描述  Express Chipset
PDF  426 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

910GL 数据表(HTML) 47 Page - Intel Corporation

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Signal Description
R
Datasheet
47
Interface
Signal Name
I/O
State During
RSTIN#
Assertion
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Host I/F
HHIT#
I/O
TERM HV
TERM HV
TRI (No VTT)
HHITM#
I/O
TERM HV
TERM HV
TRI (No VTT)
HLOCK#
I/O
TERM HV
TERM HV
TRI (No VTT)
HREQ[4:0]#
I/O
TERM HV
TERM HV
TRI (No VTT)
HTRDY#
O
TERM HV
TERM HV
TRI (No VTT)
HRS[2:0]#
O
TERM HV
TERM HV
TRI (No VTT)
HBREQ0#
I/O
TERM HV
TERM HV
TRI (No VTT)
HPCREQ#
I
TERM HV
TERM HV
TRI (No VTT)
HVREF
I
IN
IN
TRI
HRCOMP
I/O
TRI
TRI after RCOMP
TRI
20
Ω resistor
for board with
target
impedance of
60
Ω
HSWING
I
IN
IN
HSCOMP
I/O
TRI
TRI
TRI
Table 2-2. System Memory (DDR2) Reset and S3 States
Interface
Signal Name
I/O
State During
RSTIN#
Assertion
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Channel A
SCLK_A[5:0]
O
TRI
TRI
TRI
SCLK_A[5:0]#
O
TRI
TRI
TRI
SCS_A[3:0]#
O
TRI
TRI
TRI
SMA_A[13:0]
O
TRI
TRI
TRI
SBS_A[2:0]
O
TRI
TRI
TRI
SRAS_A#
O
TRI
TRI
TRI
SCAS_A#
O
TRI
TRI
TRI
SWE_A#
O
TRI
TRI
TRI
SDQ_A[63:0]
I/O
TRI
TRI
TRI
SDM_A[7:0]
O
TRI
TRI
TRI
SDQS_A[7:0]
I/O
TRI
TRI
TRI
SDQS_A[7:0]#
I/O
TRI
TRI
TRI
SCKE_A[3:0]
O
LV
LV
LV
System
Memory
(DDR2)
SODT_A[3:0]
O
LV
LV
LV



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