910GL datasheet(38/426 Pages) INTEL

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Signal Description

Datasheet

2.2

DDR/DDR2 DRAM Channel A Interface

Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.

Signal Name

Type

Description

SCLK_A[5:0]

SSTL-

2/1.8

SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its

complement SCLK_Ax# signal make a differential clock pair output. The

crossing of the positive edge of SCLK_Ax and the negative edge of its

complement SCLK_Ax# are used to sample the command and control

signals on the SDRAM.

SCLK_A[5:0]#

SSTL-

2/1.8

SDRAM Complementary Differential Clock: (3 per DIMM) These are

the complementary differential DDR/DDR2 clock signals.

SCS_A[3:0]#

SSTL-

2/1.8

Chip Select: (1 per Rank) These signals select particular SDRAM

components during the active state. There is one chip select for each

SDRAM rank.

SMA_A[13:0]

SSTL-

2/1.8

Memory Address: These signals are used to provide the multiplexed

row and column address to the SDRAM

SBS_A[2:0]

SSTL-

2/1.8

Bank Select: These signals define which banks are selected within each

SDRAM rank

DDR2: 1-Gb technology is 8 banks.

DDR: 1-Gb technology is 4 banks. SBS_A[2] is not used.

SRAS_A#

SSTL-

2/1.8

Row Address Strobe: This signal is used with SCAS_A# and SWE_A#

(along with SCS_A#) to define the SDRAM commands.

SCAS_A#

SSTL-

2/1.8

Column Address Strobe: This signal is used with SRAS_A# and

SWE_A# (along with SCS_A#) to define the SDRAM commands.

SWE_A#

SSTL-

2/1.8

Write Enable: This signal is used with SCAS_A# and SRAS_A# (along

with SCS_A#) to define the SDRAM commands.

SDQ_A[63:0]

I/O

SSTL-

2/1.8

Data Lines: SDQ_A signals interface to the SDRAM data bus.

SDM_A[7:0]

SSTL-

2/1.8

Data Mask: When activated during writes, the corresponding data

groups in the SDRAM are masked. There is one SDM_Ax signal for

every data byte lane.

SDQS_A[7:0]

I/O

SSTL-

2/1.8

Data Strobes: For DDR, the rising and falling edges of SDQS_Ax are

used for capturing data during read and write transactions. For DDR2,

SDQS_Ax and its complement SDQS_Ax# signal make up a differential

strobe pair. The data is captured at the crossing point of SDQS_Ax and

its complement SDQS_Ax# during read and write transactions.

SDQS_A[7:0]#

I/O

SSTL-1.8

Data Strobe Complements (DDR2 only): These signals are the

complementary DDR2 strobe signals.

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