910GL datasheet(37/426 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

HREQ[4:0]#

I/O

GTL+

Host Request Command: These signals define the attributes of the

request. HREQ[4:0]# are transferred at 2x rate. They are asserted by the

requesting agent during both halves of Request Phase. In the first half the

signals define the transaction type to a level of detail that is sufficient to

begin a snoop request. In the second half the signals carry additional

information to define the complete transaction type.

The transactions supported by the (G)MCH Host Bridge are defined in the

Host Interface section of this document.

HTRDY#

GTL+

Host Target Ready: This signal indicates that the target of the processor

transaction is able to enter the data transfer phase.

HRS[2:0]#

GTL+

Response Signals: These signals indicate the type of response as shown

below:

000 = Response type

001 = Idle state

010 = Retry response

011 = Deferred response

100 = Reserved (not driven by (G)MCH)

101 = Hard Failure (not driven by (G)MCH)

110 = No data response

111 = Implicit Writeback

111 = Normal data response

BSEL[2:0]

CMOS

Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on

these pins determines the expected frequency of the bus.

HRCOMP

I/O

CMOS

Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.

This signal is powered by the Host Interface termination rail (VTT).

HSCOMP

I/O

CMOS

Slew Rate Compensation: Compensation for the Host Interface.

HSWING

Host Voltage Swing: This signal provides the reference voltage used by

FSB RCOMP circuits. HSWING is used for the signals handled by

HRCOMP.

HVREF

Host Reference Voltage Reference: Voltage input for the data, address,

and common clock signals of the Host GTL interface.

910GL 数据表(PDF) 37 Page - Intel Corporation

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910GL 数据表(PDF) 37 Page - Intel Corporation

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