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3.2

Platform Configuration

In platforms that support DMI (e.g. this (G)MCH) the configuration structure is significantly

different from previous Hub architectures. The DMI physically connects the (G)MCH and the

Intel ICH6; so, from a configuration standpoint, the DMI is logically PCI bus 0. As a result, all

devices internal to the (G)MCH and the Intel ICH6 appear to be on PCI bus 0.

The ICH6 internal LAN controller does not appear on bus 0; it appears on the external PCI bus

(whose number is configurable).

The system’s primary PCI expansion bus is physically attached to the Intel ICH6 and, from a

configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and

therefore has a programmable PCI Bus number. The PCI Express Graphics Attach appears to

system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI

bus 0.

Note:

A physical PCI bus 0 does not exist and that DMI and the internal devices in the (G)MCH and

Intel ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in Figure 3-1.

Figure 3-1. Conceptual Chipset PCI Configuration Diagram

Device 1 (82915G/82915P/

82915PL GMCH only

Internal Graphics Bus 0,

(82915G/82915GV/82915G

L82910GL Device

Intel ® 82915G/ 82915GV/ 82915GL/

82915P/82915PL/82919GL (G)MCH

Processor

PCI Configuration in I/O

DRAM Interface Bus 0,

Device 0

DMI

PCI_Config_Dia

910GL 数据表(PDF) 55 Page - Intel Corporation