910GL datasheet(33/426 Pages) INTEL

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Signal Description

Datasheet

Signal Description

This chapter provides a detailed description of (G)MCH signals. The signals are arranged in

functional groups according to their associated interface. The states of all of the signals during

reset are provided in Section 2.11.

The following notations are used to describe the signal type:

GTL+

Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for

complete details. The (G)MCH integrates GTL+ termination resistors, and

supports VTT of from 0.83 V to 1.65 V (including guardbanding).

PCIE

PCI-Express interface signals. These signals are compatible with PCI Express

1.0 Signaling Environment AC Specifications and are AC coupled. The buffers

are not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2

= 1.2 V maximum. Single-ended maximum = 1.5 V.

Single-ended minimum = 0 V.

DMI

Direct Media Interface signals. These signals are compatible with PCI Express

1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers

are not 3.3 V tolerant. Differential voltage specification

= (|D+ - D-|) * 2 = 1.2 V maximum. Single-ended maximum = 1.5 V.

Single-ended minimum = 0 V.

CMOS

CMOS buffers. 1.5 V tolerant.

COD

CMOS Open Drain buffers. 2.5 V tolerant.

HVCMOS

High Voltage CMOS buffers. 2.5 V tolerant.

HVIN

High Voltage CMOS input-only buffers. 3.3 V tolerant.

SSTL-2

Stub Series Termination Logic. These are 2.6 V output capable buffers. 2.6 V

tolerant.

SSTL-1.8

Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V

tolerant.

Analog reference or output. May be used as a threshold voltage or for buffer

compensation.

910GL 数据表(PDF) 33 Page - Intel Corporation

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