910GL datasheet(117/426 Pages) INTEL

117 / 426 page

DMIBAR Registers—Direct Media Interface (DMI) RCRB

Datasheet

117

7.1.3

DMIPVCCAP2—DMI Port VC Capability Register 2

MMIO Range:

DMIBAR

Address Offset:

008h

Default Value:

00000001h

Access:

Size:

32 bits

This register describes the configuration of Virtual Channels associated with this port.

Bit

Access &

Default

Description

31:24

00h

VC Arbitration Table Offset (ATO): This field indicates that no table is present

for VC arbitration since it is fixed.

23:8

Reserved

7:0

01h

VC Arbitration Capability: This field indicates that the VC arbitration is fixed in

the root complex. VC1 is highest priority and VC0 is lowest priority.

7.1.4

DMIPVCCTL—DMI Port VC Control

MMIO Range:

DMIBAR

Address Offset:

00Ch

Default Value:

00000000h

Access:

R/W, RO

Size:

16 bits

Bit

Access &

Default

Description

15:4

Reserved

3:1

R/W

000b

VC Arbitration Select: This field indicates which VC should be programmed in

the VC arbitration table. The root complex takes no action on the setting of this

field since there is no arbitration table.

Load VC Arbitration Table (LAT): This field indicates that the table programmed

should be loaded into the VC arbitration table. This bit is defined as read/write with

always returning 0 on reads.

910GL 数据表(PDF) 117 Page - Intel Corporation

910GL 数据表(HTML) 117 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载