STA321 datasheet(56/157 Pages) STMICROELECTRONICS

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FFX

STA321

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Doc ID 15351 Rev 3

7.4

Ternary mode

The ternary mode feature is also available. It is activated by bits TERNARY_n in registers

PWMOnCFG0 beginning on page 91 (where n is the number, 1 to 4, of the output).

This feature overrides the PWM mode bits settings PM_nA and PM_nB.

Figure 33.

Ternary modulation

7.5

Minimum pulse limitation

The FFX modulator has a minimum pulse limitation feature which has a double purpose:

to limit the maximum/minimum duty cycle when the audio signal is near to full scale;

to have the commutations on the same channel outputs A and B separated by a

minimum pulse distance.

The first feature is always enabled.

The second feature is enabled with register bit PWMOnCFG0.MP_ZERO_n, where n is the

output 1 to 4. It is possible to prevent the commutations on outputs A and B to happen

exactly at the same time using bit AZPLS_n. The minimum pulse size is determined by the

number of system clock (98.304 MHz) periods programmed in bits MIN_PLS_n[3:0].

A: 10

B: 10

A: 00

B: 01

PWM mode

Phase

shift

New

phase

shift

A: 10

B: 10

A: 00

B: 01

Ternary

TERNARY_n

= 0

TERNARY_n

= 1

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