STA321 datasheet(31/157 Pages) STMICROELECTRONICS

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STA321

Clock management

Doc ID 15351 Rev 3

31/157

5.2

Peripheral clock manager

This block manages the clocks of the core processing peripherals ADC, FFX, PROC

(including memories and SAI interfaces) and SRC.

A clock divider (by 2) is attached before every block except the FFX.

Each block is attached to a global gating cell and to a dedicated one. This allows a flexible

power-consumption management because it is possible to turn off either the whole

processing chain or just a single block. The only exception is the I2C peripheral clock which

is disabled only when the device is in hardware power-down mode. In all the other cases this

clock remains active.

5.3

Fractional PLL

The PLL specifications are given in Table 6 on page 14.

Figure 12.

PLL block diagram

5.3.1

PLL block description

Phase/frequency detector (PFD)

This block compares the phase difference between the corresponding rising edges of the

F_INT and the clock coming from the loop frequency divider.

It generates voltage pulses with widths proportional to the input phase error.

Charge pump and loop filter (LPF/CPUMP)

This block converts the voltage pulses from the phase/frequency detector to current pulses

which charge the loop filter and generate the control voltage for the voltage controlled

oscillator (VCO).

Lock detect

Buffer

Loop freq. divider

LDF

PFD

VCO

LPF

cpump

IDF

Input freq. divider

Fractional

controller

DITHER

Disable

FRAC

Input

CLKIN

PLL_PWDN

LOCKP

NDIV

PLLCFG0(5-4)

PLLCFG1(7-0)

PLLCFG2(7-0)

pll_strb

pll_strbbyp

pll_fr_ctrl

PLLCFG3(5-0)

PLLCFG3(7)

PLLCFG3(6)

PLLCFG0(6)

PLLCFG0(3-0)

IDF

FVCO

PLL_CLK_in

F_INT

pll_clk_in

CLKIN

PLLCFG0[3:0]

IDF

PLL_PWDN

PLLCFG3[7]

PLL_STRB

PLL_STRBBYP

PLL_FR_CTRL

PLLCFG3[6]

PLLCFG0[6]

LOCKP

FVCO

DITHER

Disable

PLLCFG0[5:4]

FRAC

Input

NDIV

PLLCFG2[7:0]

PLLCFG1[7:0]

PLLCFG3[5:0]

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