STA321 datasheet(71/157 Pages) STMICROELECTRONICS

71 / 157 page

STA321

Serial audio interface

Doc ID 15351 Rev 3

71/157

11.4

Invalid detection

STA321 has an invalid input detection feature that can detect an invalid serial interface bit

clock or frame clock and then mute the processing channels to avoid any speaker or

headphone damage and, moreover, to avoid loud audible transients which may be

discomforting to the listener. The control is active only for the SAI input. The configuration

programmed in bits 0, 1 and 2 of register FFXCFG0 on page 82 is applicable to both SAI1

and SAI2 whilst the checks are independent for each interface. The mute on the processing

channel is asserted depending on the input interface mapping.

Figure 50 shows the invalid detection schematic. Here, two different checks are available.

The first one is enabled by register bit FFXCFG0.BAD_CKS_M and evaluates the ratio of

BICLK and LRCLK. The resulting number must be the same as that written in bits

S2Pn_BOS (for example, 32 * fS or 64 * fS) in registers SAI_IN1_CFG1 on page 123 and

SAI_IN2_CFG1, otherwise the channels are muted.

The second check is enabled by register bit FFXCFG0.MIS_BICK_M and is related to the

presence of BICLK. Basically, a 8-bit watchdog counter decrements, starting from 0xFF, with

each edge of clk_proc. The counter is reset to 0xFF at each BICLK edge; so, if the

watchdog counter ever reaches 0x00, a missing bit clock error is signalled and the mute

command is issued.

Figure 50.

Invalid input detection schematic

BICLKI1

LRCLKI1

BICLKI2

LRCLKI2

Ratio

calculator

Ratio

calculator

alive?

S2P2_BOS

S2P1_BOS

clk_proc

MIS_BICK_M

BAD_CKS_M

MUTE0

MUTE1

MUTE2

MUTE3

MUTE0

MUTE1

MUTE3

MUTE2

mute ch0

mute ch1

mute ch2

mute ch3

SRC1_INSEL

SRC2_INSEL

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