STA321 datasheet(27/157 Pages) STMICROELECTRONICS

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STA321

Power-up and power-down sequences

Doc ID 15351 Rev 3

27/157

4.3.2

Full power-down

In this case the device is put into a full power-down mode.

This implies lower power consumption than the mild mode, but has a drawback in that it

takes longer to execute.

Initial conditions

FFX_ULCK_PLL = 10

CMP_EN_N = 1

DC_STBY_EN = 1

Going into power-down:

This mode differs from the previous one by an additional step at the end of the power-

down procedure and at the beginning of the power-up:

Embedded amplifier (EA) and CMOS bridge (CB) volume are set to mute (the length of

this step changes according to the fade-out ramp configuration).

EA and CB are put into power-down.

After the acknowledge signals (EA is in power-down and CB is in power-down) are

received:

All peripherals are turned off (regardless the register settings).

PLL clock is bypassed, the system clock (sys_clk in Figure 11 on page 29) is XTI.

All clocks are shut down.

DC regulator is put into standby mode. After this point the device is in a very low power

consumption mode.

Returning to normal mode:

After the release of pin STBY, the power-up procedure will take place:

DC regulator is set to operational mode

After the acknowledge signal (DCAOK) from the DC regulator is received:

All clocks are turned on.

All peripherals are restored to the status based on their relative register settings.

If the PLL clock was the system clock it is selected again after the locking time.

The EA and the CB execute the fade-in procedure before being ready to be used (the

length of this step changes according to the fade-in ramp configuration).

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