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STA321 数据表(PDF) 39 Page - STMicroelectronics |
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STA321 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 157 page ![]() STA321 Digital processing stage Doc ID 15351 Rev 3 39/157 6.6 Biquads The biquads are based on the following equation and is shown diagramatically in Figure 20. Y[n] = b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2] where Y[n] represents the output and X[n] represents the input. Fractional multipliers are 24-bit signed with coefficient values in the range -1 (0xFFFFFF) to +1 (0x7FFFFF). Figure 20. Biquad filter 6.6.1 Presets By default all the biquads values in RAM are set to give a bypass function; in actual fact, the signal passes through unchanged. The coefficients for this are: a1 / 2 = 0, a2 / 2 = 0, b0 / 2 = 0.5 (0x400000), b1 / 2 = 0, b2 / 2 = 0. 6.7 High-pass filter The standard high-pass filter is provided by the STA321 Figure 21. High-pass filter frequency response 2 b0/2 + b1/2 2 Z -1 + b2 Z -1 + 2 -a1/2 -a2 Z -1 Z -1 10 0 10 1 10 2 10 3 10 4 10 5 −30 −25 −20 −15 −10 −5 0 Freq. [Hz] High Pass Filter |
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