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STA321 数据表(PDF) 21 Page - STMicroelectronics |
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STA321 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 157 page  STA321 Power-up and power-down sequences Doc ID 15351 Rev 3 21/157 4.2 Software power-down mode The software power-down is obtained by configuring the appropriate I2C registers. In order to obtain flexibility every peripheral has its independent, standby signal and several gating clock cells are available. Obviously, the I2C peripheral can not be turned off in this mode, otherwise the device can recover from the power-down state only via the reset pin. In the table below EA is embedded amplifier and CB is CMOS bridge. For complete information this table must be used in conjunction with Chapter 14: Register description on page 77. Table 9. Startup timings Parameter Description Min Typ Max Unit DC reg. power-up time Start up time of the DC Regulator after connecting the power - - 300 µs Device in reset mode Must be greater than (VDD time + DC reg. power-up time) - --µs Table 10. Configuration example Register address Value Description 0xC9 0x00 Remove PLL bypass 0xCA 0x00 Headphone detection polarity = 0 0xB8 0x4A Configure SAI output: SAI_out1 = SAI_in1, SAI_out2 = SAI_in2 0xB7 0x38 SRC source select: SRC1 = ADC, SRC2 = ADC 0xC6 0x02 ADC clock on 0xB2 0xF3 I2S configuration 0xC8 0x21 Core clock on, SAI/ADC audio set to 32 kHz - 48 kHz range 0xB2 0xD3 SAI_out: output enabled 0xA0 0x00 Soft volume removed 0x00 0x00 Remove bridge 3-state Table 11. Registers for power-down Description Register bit Address Put EA in standby FFXCFG1[7] 0x00 on page 81 Put CB in standby FFXCFG1[6] 0x00 Put PLL in standby PLLPFE[5] 0xC4 on page 132 Put ADC in standby ADCCFG0[3] 0xC6 on page 133 Turn core clock off MISC[0] 0xC8 on page 135 Turn ADC clock off ADCCFG0[1] 0xC6 |
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