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STA321 数据表(PDF) 15 Page - STMicroelectronics |
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STA321 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 157 page  STA321 Electrical specifications Doc ID 15351 Rev 3 15/157 Amplifier (CMOS bridge) η Output power efficiency - - 90 - % PHPOUT Output power in HP mode with THD = 1% 3.3-V supply RL = 32 Ω -41 - mW Output power in HP mode with THD = 10% 3.3-V supply RL = 32 Ω -53 - SNR Signal to noise ratio 20 Hz to 20 kHz - 75 - dB THD + N Total harmonic distortion plus noise RL = 32 Ω, HP mode 0 dBFs In - 0.3 - % -6 dBFs In - 0.05 - DR Dynamic range A-weighted - 80 - dB ISTBYP Current in standby, pins VCCx - - 2 - µA IDDP Operating current, pins VCCx No LC filter, no load, PWM at 50% duty-cycle -1 - mA IDDPD Pre-drive supply current in operation, pin VCC33 No load, PWM at 50% duty-cycle - 250 350 µA tR Driver rise time, pins OUT1-3 Resistive load, see Figure 3 -5 - ns tF Driver fall time, pins OUT1-3 Resistive load, see Figure 3 -5 - ns RDSON Headphone output stage N/P MOS on-resistance - - 500 700 m Ω IOCH Over-current limit for OUT1-3 to VCCx short circuit - - 1.88 - A IOCL Over-current limit for OUT1-3 to ground short circuit - - 1.72 - A PLL ISTDBYPLL PLL supply current in standby - - 20 - µA IDDPLL PLL supply current in operation - - 0.4 1.0 mA fCLKIN_Range Input clock frequency range - 2.048 - 49.152 MHz DutyCLKIN Input clock duty cycle - 40 - 60 % tCLKIN_RF Input clock rise/fall time - - - 0.2 ns fF_INT PFD input clock frequency PLL_FR_CTRL = 1 2.048 - 12.288 MHz fVCO_Range Clock out range - 65.536 - 98.304 MHz DutyVCO Clock out duty cycle - 35 - 65 % TLOCK Lock time - - - 200 µs Table 6. Electrical specifications (continued) Symbol Parameter Test conditions Min Typ Max Unit |
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