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STA321 数据表(PDF) 34 Page - STMicroelectronics |
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STA321 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 157 page ![]() Digital processing stage STA321 34/157 Doc ID 15351 Rev 3 6 Digital processing stage 6.1 Signal processing flow The STA321 provides 4 channels of audio signal processing. The block diagram is shown in the following figure. Figure 13. Processing flow Left and right channels coming from the two serial audio interfaces and ADC (left and right channels) are fed into the selection multiplexer (controlled by register SRCINSEL on page 128), so that each channel can be connected to any desired processing chain. The four channels are then sample rate converted to the fixed internal sampling rate. Pre mix, EQ/tone processing, programmable delay, post mix, and volume/limiter make up the STA321 signal processing chain. Figure 14. Processing data multiplexer Bq0 Bq12 Bq12 Bq12 Bq12 EQ - tone control 13 biquads kZ-1 kZ-1 kZ-1 kZ-1 Delay - G2 - G0 - G1 - G3 Vol 3 Vol 2 Vol 1 Vol 0 Volume control Limiter rate converter Sample Bq0 Bq0 Bq0 Pre scaler 32 SAI_in1 00 16 ADC 01 32 SAI_in2 10 24 SRCINSEL[7:6] 24 SRC1 ch0_in ch1_in PROC ch0 PROC ch1 PROC ch2 PROC ch3 24 24 24 32 SAI_in1 00 16 ADC 01 32 SAI_in2 10 20 24 SRC2 ch2_in ch3_in ch0_out ch1_out ch2_out ch3_out 20 20 20 SRCINSEL[5:4] FFX 2-channel signal 1-channel signal To SAI_out multiplexers Processing |
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