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STA321 数据表(PDF) 30 Page - STMicroelectronics |
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STA321 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 157 page  Clock management STA321 30/157 Doc ID 15351 Rev 3 5.1 System clock Figure 11 above shows the STA321 clock management scheme with all the major clocks. As can be seen, the system clock (sys_clk) is selected from one of three sources by using register PLLB on page 136: an external clock BICLKI1 (default) an external clock XTI or MCLK (the unused one must, however, be set to 0) the internal PLL. If the PLL is used there are some design constraints: pll_clk_in_i must be in the range: 2.048 MHz to 49.152 MHz pll_clk_out must be in the range: 65.536 MHz to 98.304 MHz. The sys_clk is routed to the peripherals through the clock manager section. 5.1.1 Configuration example This is an example of the PLL register setup. It is assumed that every peripheral is already configured and working correctly. There are other configuration examples to help you get started please refer to other chapters and also to Chapter 14: Register description on page 77 in order to get all the necessary and complementary details. Starting with MCLK as system clock switching to PLL as source Table 15. Clock characteristics Symbol Parameter Min Typ Max Unit fMCLK_Range Input clock frequency range 2.048 - 49.152 MHz DutyMCLK Input clock duty cycle 40 - 60 % tMCLK_RF Input clock rise/fall time - - 0.2 ns fXTI_Range Input clock frequency range 2.048 - 49.152 MHz DutyXTI Input clock duty cycle 40 - 60 % tXTI_RF Input clock rise/fall time - - 0.2 ns fBICLK1_Range Input clock frequency range 2.048 - 49.152 MHz DutyBICLK1 Input clock duty cycle 40 - 60 % tBICLK1_RF Input clock rise/fall time - - 0.2 ns fCLKOUT_Range Output clock frequency range - - 49.152 MHz Table 16. Register setup to provide sys_clk from MCLK to PLL Register Address Value Description PLLPFE 0xC4 0x80 Safety operational mode: automatic use of MCLK (or XTI) as system clock if the PLL is not locked PLLB 0xC9 0x00 Remove the PLL bypass and use its clock as system |
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