STA321 datasheet(61/157 Pages) STMICROELECTRONICS

61 / 157 page

STA321

CMOS power stage

Doc ID 15351 Rev 3

61/157

The CMOS bridge power rating can be calculated using the following formulas:

P (<1%) = (RL / 2) * (M * VCC / 2 / (RL + 2 * RDS))

2 for BTL

P (<1%) = (RL / 2) * (M * VCC / 2 / (RL + RDS))

2 for single ended

P (10%) = 1.28 * P(<1%)

where RDS is composed of the MOST RDSON and the board and connector parasitic

resistances (including power supplies and coils) and M is the modulation index obtained

from

M = 1 - 2 * (MIN_PLS_n + 1) / fclk_ffx / τS

where MIN_PLS_n is the value in register PWMOnCFG0 for channel n, fclk_ffx is the

frequency of the FFX clock and

τS is the PWM clock period (384 kHz or 768 kHz selected by

For the CMOS bridge, MIN_PLS_n can be set to 0; this gives M = 0.9922.

The analog pop_free function is available in the CMOS bridge circuit by setting the

appropriate bridge start-up as per Table 26. The CMOS bridge enable and pop-free signals

are generated from the three signals Powerdown, Tristate and PopFree provided by the

digital core and controlled/configured through register bits FFXCFG1.CB_STBY,

FFXCFG1.CB_TRISTn and PFEFAULT.PFEn for the three outputs, n = 1 to 3.

Figure 37.

Analog pop-free schematic

Table 25.

Power output (at 1% THD) in headphone mode

Load, RL in Ω

Power, P in mW (for 3.3-V supply)

PFE & not(Tristate) & Powerdown

OutN

GNDx

VCCx

STA321 数据表(PDF) 61 Page - STMicroelectronics