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STA321 数据表(PDF) 20 Page - STMicroelectronics |
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STA321 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 157 page  Power-up and power-down sequences STA321 20/157 Doc ID 15351 Rev 3 4 Power-up and power-down sequences 4.1 Device power-up After providing the power supply to the device, it is necessary to wait until the DC regulator PWUP time has elapsed before the device can be set up and used for normal operations. (see Figure 7). Figure 7. Startup sequence Table 8. Power-up signal description Signal/pin Type Description VDDIO Supply Power supply of the digital pads (= VDDIO1,2) VDD_REG Supply Power supply of the system core (= VDD_REG1,2) PVDD Supply Power supply of the PLL STBY In (digital) External standby signal provided by the user RSTN In (digital) External reset signal provided by the user PWDN Internal Power-down of the DC regulator cell, controlled by the core A. OK Internal DC regulator status, when active the 1.8 V is provided to the core I2C read In (I2C) Configuration commands coming to the I2C interface I2C clock Internal I2C peripheral clock XTI/MCLK In (digital) Clock input source DC reg. PWUP time Device in reset mode Vdd ramp RSTN (active L) STBY (active H) DC Reg. PWDN (active High) (active High) DC Reg. A. OK I2C Writings I2C CLK XTI /MCLK VDDIO VDDREG PVDD 3v3 2v2 User configuration via I 2C VVDDIO VVDD_REG VPVDD STBY (active H) RSTN (active L) PWDN (active H) A.OK (active H) I 2 C read I 2 C clock XTI / MCLK |
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