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STA321 数据表(PDF) 82 Page - STMicroelectronics |
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STA321 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 157 page  Register description STA321 82/157 Doc ID 15351 Rev 3 FFXCFG0 Address: 0x01 Type: RW Reset: 0x07 Description: 76 54 3 2 1 0 MUTE3 MUTE2 MUTE1 MUTE0 PWM00_3A BAD_IN_M BAD_CKS_M MIS_BICK_M [7] MUTE3 0: normal behaviour 1: force the mute in the channel 3 [6] MUTE2 0: normal behaviour 1: force the mute in the channel 2 [5] MUTE1 0: normal behaviour 1: force the mute in the channel 1 [4] MUTE0 0: normal behaviour 1: force the mute in the channel 0 [3] PWM00_3A 0: output PWM00 is driven by FFX (default) 1: output PWM00 comes from FFX output PWM3A and is not sensitive to bridge power-down or 3-state states [2] BAD_IN_M Depending on the bit 0 and bit 1 settings 0: mute with a ramp 1: mute instantaneously [1] BAD_CKS_M 0: FFX not muted 1: FFX muted if biclk and lrclk do not meet the specification [0] MIS_BICK_M 0: FFX not muted 1: FFX will be muted if biclk is missing |
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