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STA321 数据表(PDF) 136 Page - STMicroelectronics |
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STA321 数据表(HTML) 136 Page - STMicroelectronics |
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136 / 157 page ![]() Register description STA321 136/157 Doc ID 15351 Rev 3 PLLB Address: 0xC9 Type: RW Reset: 0x80 Description: See also Figure 11: Clock management scheme on page 29 76 54 32 10 PLL_BYP Reserved ADC_CLKSEL Reserved P2S1_CLKSEL Reserved P2S2_CLKSEL Reserved [7] PLL_BYP 0: PLL not bypassed 1: PLL bypassed [6] Reserved [5] ADC_CLKSEL 0: clk_adc / 4 1: pll_clk_in [4] Reserved [3] P2S1_CLKSEL 0: processing clock 1: pll_clk_in [2] Reserved [1] P2S2_CLKSEL 0: processing clock 1: pll_clk_in [0] Reserved |
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