BQ28Z560-R1 datasheet(51/60 Pages) TI1

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ADDR[6:0]

CMD[7:0]

DATA[7:0]

... N

ADDR[6:0]

CMD[7:0]

N P

ADDR[6:0]

CMD[7:0]

DATA[7:0]

ADDR[6:0]

CMD[7:0]

DATA[7:0]

A P

ADDR[6:0]

DATA[7:0]

N P

ADDR[6:0]

CMD[7:0]

A Sr

ADDR[6:0]

DATA[7:0]

N P

ADDR[6:0]

CMD[7:0]

A Sr

ADDR[6:0]

DATA[7:0]

...

DATA[7:0]

N P

(d)

(c)

(a)

(b)

HostGenerated

FuelGaugeGenerated

bq28z560-R1

www.ti.com

SLUSBD3 – APRIL 2013

HDQ serial communication is normally initiated by the host processor sending a break command to the

bq28z560-R1. A break is detected when the DATA pin is driven to a logic-low state for a time t(B) or greater. The

DATA pin should then be returned to its normal ready high logic state for a time t(BR). The bq28z560-R1 is now

ready to receive information from the host processor.

The bq28z560-R1 is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.

HDQ HOST INTERRUPTION FEATURE

The default bq28z560-R1 behaves as an HDQ slave only device. If the HDQ interrupt function is enabled, the

bq28z560-R1 is capable of mastering and also communicating to a HDQ device. There is no mechanism for

negotiating who is to function as the HDQ master and care must be taken to avoid message collisions. The

interrupt is signaled to the host processor with the bq28z560-R1 mastering an HDQ "message." This message is

a fixed message that will be used to signal the interrupt condition. The message itself is 0x80 (slave write to

condition. The HDQ interrupt function is not public and needs to be enabled by command.

When the SET_HDQINTEN subcommand is received, the bq28z560-R1 will detect any of the interrupt conditions

and assert the interrupt at 1-s intervals until the CLEAR_HDQINTEN command is received or the count of

HDQHostIntrTries has lapsed.

The number of tries for interrupting the host will be determined by the data flash parameter named

Configuration.Register.HDQHostIntrTries.

The HDQ host interrupt is triggered by the settings in the bat alert feature. The HDQ host interrupt signal will be

asserted when the Flags()[ALRT] bit is triggered, based on the settings in the BatAlertConfig() register.

I2C INTERFACE

The gas gauge supports the standard I2C read, incremental read, 1-byte write quick read, and functions. The 7-

bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit

device address is therefore 0xAA or 0xAB for write or read, respectively.

(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).

The "quick read" returns data at the address indicated by the address pointer. The address pointer, a register

internal to the I2C communication engine, increments whenever data is acknowledged by the bq28z560-R1 or

the I2C master. "Quick writes" function in the same manner and are a convenient means of sending multiple

bytes to consecutive command locations (such as 2-byte commands that require two bytes of data).

Attempt to write a read-only address (NACK after data sent by master):

Attempt to read an address above 0x7F (NACK command):

Attempt at incremental writes (NACK all extra data bytes sent):

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