BQ28Z560-R1 datasheet(10/60 Pages) TI1

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SCL

SDA

tsu (STA)

td (STA)

tsu (DAT)

th(DAT)

tw(H)

tw(L)

t(BUF)

tsu(STOP)

REPEATED

START

STOP

START

bq28z560-R1

SLUSBD3 – APRIL 2013

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2C SERIAL COMMUNICATION TIMING CHARACTERISTICS

TA = –40 to +85ºC, VBAT = 2.7 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT = 3.6 V (unless otherwise noted).

Capacitance on serial interface pins SCL and SDA are 10 pF unless otherwise specified

(1).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SCL/SDA rise time

300

SCL/SDA fall time

300

tw(H)

SCL pulse width (high)

600

tw(L)

SCL pulse width (low)

1.3

μs

tsu(STA)

Setup for repeated start

600

td(STA)

Start to first falling edge of SCL

600

tsu(DAT)

Data setup time

μs

th(DAT)

Data hold time

tsu(STOP)

Setup time for stop

600

Bus free time between stop and

t(BUF)

1.3

μs

start

f(SCL)

Clock frequency

100

kHz

(1)

Parameters specified by worst-case test program execution in FAST mode.

Figure 5. I2C Serial Communication Timing

2C BUS COMMUNICATION

The 2-wire communication bus supports a slave-only device in a single- or multi-slave configuration with a single-

or multi-master configuration. The device can be part of a shared bus by the unique setting of the 7-bit slave

address. The 2-wire communication is bi-directional, consisting of a serial data line (SDA) and serial clock line

(SCL). In RECEIVE mode, the SDA terminal operates as an input; whereas, when the device is returning data to

the master, the SDA operates as an open drain output with an external resistive pull-up. The master device

controls the initiation of the transaction on the bus line.

Data Transfer: Each data bit is transferred during an SCL clock cycle (transition from low-to-high and then high-

to-low). The data signal on the SDA (logic level) must be stable during the high period of the SCL clock pulse. A

change in the SDA logic when SCL is high is interpreted as a START or STOP control signal. If a transfer is

interrupted by a STOP condition, the partial byte transmission shall not be latched. Only the prior messages

transmitted and acknowledged are latched.

Data Format: The data is an 8-bit format with the most significant bit (MSB) first, and the least significant bit

(LSB) followed by an Acknowledge bit. If the slave cannot receive or transmit any byte of data until it services a

priority interrupt, it can pull the SCL line low to force the master device into wait state. The slave, once ready to

resume data transfer, can release the SCL line (get out of wait state).

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