BQ28Z560-R1 datasheet(11/60 Pages) TI1

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bq28z560-R1

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SLUSBD3 – APRIL 2013

Bus Idle: The bus is considered idle or busy when no master device has control of this device. The SDA and

SCL lines are high when the bus is idle. The appropriate method to go into the STOP condition is to ensure the

bus returns to idle state.

START (S) and STOP (P) Conditions: To initiate communications, the master device transitions the SDA line

from high-to-low when the SCL is high. Conversely, to STOP the communication, the SDA goes low-to-high

when the SCL is high. To continue communication without terminating one transaction and beginning another, a

repeated START (Sr) method can be used without a STOP condition being initiated. These are the only

conditions (START or STOP) when SDA transitions when SCL is high.

Acknowledge Bits: An Acknowledge bit (A) is required after each data transfer byte to ensure correct

communications. This occurs when the receiving device pulls the SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and keeps it low until the SCL returns low. There is also a No-

Acknowledge bit (N), which occurs when the receiver releases the SDA line (high) before the rising edge of

acknowledge-related clock pulse, and maintains the SDA line high until SCL returns low. The Acknowledge bit

indicates if a successful data transfer has occurred between the master and slave device. Monitoring this bit also

indicates an unsuccessful data transfer due to the receiving device being busy or as a system fault occurrence.

Communication Format

A START command immediately followed by a STOP command is an illegal format.

MSB

Slave Address

R/W

Data

S = START Command

R/W = Read from slave device ("1") or Write to slave device ("0")

A = Acknowledge bit

P = STOP Command

Slave Address = 7-bit address field for register address

Data = 8-bit data field

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BQ28Z560-R1 数据表(PDF) 11 Page - Texas Instruments