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BQ28Z560-R1 数据表(PDF) 52 Page - Texas Instruments |
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BQ28Z560-R1 数据表(HTML) 52 Page - Texas Instruments |
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52 / 60 page ![]() A A S 0 ADDR[6:0] CMD[7:0] Sr 1 ADDR[6:0] A DATA [7:0] A DATA [7:0] P N A A S A 0 P ADDR[6:0] CMD[7:0] DATA [7:0] DATA [7:0] A 66ms A A S 0 ADDR[6:0] CMD[7:0] Sr 1 ADDR[6:0] A DATA [7:0] A DATA [7:0] A DATA [7:0] A DATA [7:0] P N Waitingtimebetweencontrolsubcommandandreadingresults Waitingtimebetweencontinuousreadingresults 66ms 66ms S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA[7:0] A ... DATA[7:0] N P Address 0x7F DataFrom addr0x7F DataFrom addr0x00 bq28z560-R1 SLUSBD3 – APRIL 2013 www.ti.com Incremental read at the maximum allowed read address: The I2C engine releases both SDA and SCL if the I2C bus is held low for t(BUSERR). If the gas gauge was holding the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines low, the I2C engine enters the low-power SLEEP mode. I2C Timeout The I2C engine will release both SDA and SCL if the I2C bus is held low for about 2 s. If the bq28z560-R1 was holding the lines, releasing them will free the master to drive the lines. I2C Command Waiting Time To ensure getting the correct results of a command with the 400 KHz I2C operation, a proper waiting time should be added between issuing the command and reading results. For subcommands, the following diagram shows the waiting time required between issuing the control command and reading the status with the exception of the checksum command. A 100-ms waiting time is required between the checksum command and reading result. For read-write standard commands, a minimum of 2 s is required to get the result updated. For read-only standard commands, there is no waiting time required, but the host should not issue all standard commands more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer. The I2C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed during the flash updates. There can be up to a 270-ms clock stretch after the OCV command is issued. 52 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq28z560-R1 |
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