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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITE20F2 数据表(PDF) 60 Page - STMicroelectronics |
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ST7LITE20F2 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 166 page  Power saving modes ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 60/166 Doc ID 8349 Rev 5 Figure 29. AWUF halt timing diagram Figure 30. AWUF mode flowchart 1. WDGHALT is an option bit (see Section 15.1: Option bytes for more details). 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUF interrupt and some specific interrupts can exit the MCU from HALT mode (such as external AWUF interrupt fCPU Run mode HALT mode 256 or 4096 tCPU Run mode fAWU_RC Clear by software tAWU Reset Interrupt (3) Y N N Y CPU Main osc Peripherals (2) I[1:0] bits OFF OFF 10 OFF Fetch RESET vector or service interrupt CPU Main osc Peripherals I[1:0] bits ON OFF XX (4) ON CPU Main osc Peripherals I[1:0] bits ON ON XX (4) ON 256 or 4096 CPU clock delay (5) Watchdog ENABLE DISABLE WDGHALT (1) 0 Watchdog reset 1 cycle AWU RC osc ON AWU RC osc OFF AWU RC osc OFF HALT instruction (Active-halt disabled) (AWUCSR.AWUEN=1) |
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