ST7LITE20F2 datasheet(98/166 Pages) STMICROELECTRONICS

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On-chip peripherals

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Doc ID 8349 Rev 5

Figure 47. Clearing the WCOL bit (write collision flag) software sequence

Writing to the SPIDR register instead of reading it does not reset the WCOL bit

Single master and multimaster configurations

There are two types of SPI systems:

Single master system

Multimaster system.

Single master system

A typical single master system may be configured, using a device as the master and four

devices as slaves (see Figure 48).

The master device selects the individual slave devices by using four pins of a parallel port to

control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the master device ports will be forced to be

inputs at that time, thus disabling the slave devices.

Note:

To prevent a bus conflict on the MISO line the master allows only one active slave device

during a transmission.

For more security, the slave device may respond to the master with the received data byte.

Then the master will receive the previous byte back from the slave device if all MISO and

MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with

command fields.

Multi-master system

A multi-master system may also be configured by the user. Transfer of master control could

be implemented using a handshake method through the I/O ports or by an exchange of

code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the SPICR register and

the MODF bit in the SPICSR register.

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPICSR

Read SPIDR

2nd Step

SPIF =0

WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

Read SPICSR

Read SPIDR

RESULT

ST7LITE20F2 数据表(PDF) 98 Page - STMicroelectronics

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