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ST7LITE20F2 数据表(PDF) 69 Page - STMicroelectronics |
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ST7LITE20F2 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 166 page ![]() ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 I/O ports Doc ID 8349 Rev 5 69/166 Note: On ports where the external interrupt capability is selected using the EISR register, the configuration will be as follows: Interrupt ports Open drain output 1 0 Push-pull output 1 1 Table 27. Port configuration (standard ports) Port Pin name Input Output OR = 0 OR = 1 OR = 0 OR = 1 Port A PA7:0 Floating Pull-up Open drain Push-pull Port B PB6:0 Floating Pull-up Open drain Push-pull Table 26. Ports PA7:0, PB6:0 (continued) Mode DDR OR Table 28. Port configuration (Interrupt ports) Port Pin name Input Output OR = 0 OR = 1 OR = 0 OR = 1 Port A PA7:0 Floating Pull-up interrupt Open drain Push-pull Port B PB6:0 Floating Pull-up interrupt Open drain Push-pull Table 29. Ports where the external interrupt capability selected using the EISR register Mode DDR OR Floating input 0 0 Pull-up interrupt input 0 1 Open drain output 1 0 Push-pull output 1 1 Table 30. I/O port register map and reset values Address (Hex.) Register label 7654321 0 0000h PADR Reset value MSB 1111111 LSB 1 0001h PADDR Reset value MSB 0000000 LSB 0 0002h PAOR Reset value MSB 0100000 LSB 0 |
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