ST7LITE20F2 datasheet(86/166 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

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Doc ID 8349 Rev 5

Figure 40. Lite timer 2 block diagram

11.3.3

Functional description

Timebase counter 1

The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it

starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the

counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two

counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is

generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1

Input capture

The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1

after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the

ICF bit is set and the LTICR1 register contains the MSB of Counter 1. An interrupt is

generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

LTCSR1

8-bit timebase

8-bit

fLTIMER

LTIC

fOSC/32

TB1F

TB1IE

ICF

ICIE

LTTB1 interrupt request

LTIC interrupt request

LTICR

Input capture

1 or 2 ms

Timebase

(@ 8MHz

fOSC)

To 12-bit AT TImer

fLTIMER

LTCSR2

TB2F

TB2IE

LTTB2

8-bit timebase

8-bit autoreload

LTCNTR

LTARR

counter 2

counter 1

Interrupt request

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