ST7LITE20F2 datasheet(74/166 Pages) STMICROELECTRONICS

74 / 166 page

On-chip peripherals

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

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Doc ID 8349 Rev 5

11.2.2

Main features

●

12-bit upcounter with 12-bit autoreload register (ATR)

●

Maskable overflow interrupt

●

Generation of four independent PWMx signals

●

Frequency 2 kHz-4 MHz (@ 8 MHz fCPU)

–

programmable duty-cycles

–

polarity control

–

programmable output modes

–

maskable Compare interrupt

●

Input capture

–

12-bit input capture register (ATICR)

–

triggered by rising and falling edges

–

maskable IC interrupt.

Figure 34. Block diagram

11.2.3

Functional description

PWM mode

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx

output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the

PWMCR register.

ATCSR

CMPIE

OVFIE

OVF

CK0

CK1

ICIE

ICF

12-bit autoreload register

12-bit upcounter

CMPF2

CMPF1

CMPF3

CMPF0

CMP

request

OVF interrupt

request

fCPU

ATIC

12-bit input capture register

IC interrupt

request

ATR

ATICR

fCOUNTER

CNTR

32 MHz

(1 ms

fLTIMER

@ 8MHz)

CMPFx bit

polarity

OPx bit

PWMx

Comp-

pare

fPWM

OEx bit

4 PWM channels

interrupt

timebase

DCR0H

DCR0L

Preload

on OVF Event

12-bit duty cycle value (shadow)

if TRAN=1

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