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ST7LITE20F2 数据表(PDF) 81 Page - STMicroelectronics |
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ST7LITE20F2 数据表(HTML) 81 Page - STMicroelectronics |
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81 / 166 page ![]() ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Doc ID 8349 Rev 5 81/166 Autoreload register (ATRL) Read / Write Reset Value: 0000 0000 (00h) i PWM output control register (PWMCR) Read/Write Reset Value: 0000 0000 (00h) ● Bits 7:0 = OE[3:0] PWMx output enable These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx output alternate function disabled: I/O pin free for general purpose I/O after an overflow event. 1: PWM mode enabled PWMx control status register (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) ● Bits 7:2 = Reserved, must be kept cleared ● Bit 1 = OPx PWMx Output Polarity This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted 1: The PWM signal is inverted ● Bit 0 = CMPFx PWMx Compare Flag This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the DCRx register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value 7 0 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 7 0 0OE30OE2 0OE10OE0 7 6 0 000 00 0 OPx OE0 |
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