ST7LITE20F2 datasheet(96/166 Pages) STMICROELECTRONICS

96 / 166 page

On-chip peripherals

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

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Doc ID 8349 Rev 5

Figure 46 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.

The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the

MISO pin, the MOSI pin are directly connected between the master and the slave device.

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Figure 46. Data clock timing diagram

Note:

This figure should not be used as a replacement for parametric information. Refer to the

Section 13: Electrical characteristics.

11.4.5

Error Flags

Master mode fault (MODF)

Master mode fault occurs when the master device has its SS pin pulled low.

When a Master mode fault occurs:

The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.

The SPE bit is reset. This blocks all output from the Device and disables the SPI

peripheral.

The MSTR bit is reset, thus forcing the Device into slave mode.

SCK

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA =1

MSBit

Bit 6

Bit 5

Bit 4

Bit3Bit 2Bit 1

LSBit

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

CPHA =0

(from slave)

(CPOL = 1)

SCK

(CPOL = 0)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

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