ST7LITE20F2 datasheet(36/166 Pages) STMICROELECTRONICS

36 / 166 page

Supply, reset and clock management

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

36/166

Doc ID 8349 Rev 5

Figure 13. Clock management block diagram

7.4

Multi-oscillator (MO)

The main clock of the ST7 can be generated by four different source types coming from the

multioscillator block (1 to 16MHz or 32kHz):

●

an external source

●

5 crystal or ceramic resonator oscillators

●

an internal high frequency RC oscillator.

Each oscillator is optimized for a given frequency range in terms of consumption and is

selectable through the option byte. The associated hardware configurations are shown in

Table 7.

Note:

Refer to Section 13: Electrical characteristics for more details.

External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle

has to drive the OSC1 pin while the OSC2 pin is tied to ground.

CR4

CR7

CR0

CR1

CR2

CR3

CR6

CR5

RCCR

fOSC

MCCSR

SMS

MCO

fCPU

To CPU and

peripherals

(1ms timebase @ 8 MHz fOSC)

/32 divider

fOSC

fOSC/32

fOSC

fLTIMER

Lite timer 2 counter

8-bit

at TIMER 2

12-bit

PLL

8 MHz -> 32 MHz

fCPU

CLKIN

OSC2

CLKIN

Tunable

oscillator

1% RC

PLL 1 MHz -> 8 MHz

PLL 1 MHz -> 4 MHz

RC OSC

PLLx4x8

divider

Option bits

Osc,PLLoff,

OSCRANGE[2:0]

OSC

1-16 MHZ

or 32 kHz

CLKIN

/OSC1

OSC

divider

OSC/2

CLKIN/2

Option bits

Osc,PLLoff,

OSCRANGE[2:0]

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