ST7LITE20F2 datasheet(79/166 Pages) STMICROELECTRONICS

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

On-chip peripherals

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11.2.6

Timer control status register (ATCSR)

Read / Write

Reset value: 0x00 0000 (x0h)

●

Bit 7 = Reserved.

●

Bit 6 =

ICF Input capture flag

This bit is set by hardware and cleared by software by reading the ATICR register (a

read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not

change the bit value.

0: No input capture

1: An input capture has occurred

●

Bit 5 =

ICIE IC interrupt enable

This bit is set and cleared by software.

0: Input capture interrupt disabled

1: Input capture interrupt enabled

●

Bits 4:3 =

CK[1:0] Counter clock selection

These bits are set and cleared by software and cleared by hardware after a reset. They

select the clock frequency of the counter.

●

Bit 2 =

OVF Overflow flag

This bit is set by hardware and cleared by software by reading the TCSR register. It

indicates the transition of the counter from FFFh to ATR value.

0: No counter overflow occurred

1: Counter overflow occurred

●

Bit 1 =

OVFIE Overflow interrupt enable

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled.

1: OVF interrupt enabled.

●

Bit 0 =

CMPIE Compare interrupt enable

This bit is read/write by software and cleared by hardware after a reset. It can be used

ICF

ICIE

CK1

CK0

OVF

OVFIE

CMPIE

Table 35.

Counter clock selection

CK1

CK0

OFF

fLTIMER (1 ms timebase @ 8 MHz)

(1)

PWM mode and Output Compare modes are not available at this frequency.

fCPU

32 MHz (2)

ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input

Capture mode at this frequency.

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