ST7LITE20F2 datasheet(38/166 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

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Doc ID 8349 Rev 5

7.5

Reset sequence manager (RSM)

7.5.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 15: Reset

block diagram:

●

External RESET source pulse

●

Internal LVD RESET (low voltage detection)

●

Internal WATCHDOG RESET

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1: Illegal opcode reset for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic RESET sequence consists of 3 phases as shown in Figure 14:

●

Active Phase depending on the RESET source

●

256 or 4096 CPU clock cycle delay (see table below)

●

RESET vector fetch.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay is

automatically selected depending on the clock source chosen by option byte:

The RESET vector fetch phase duration is 2 clock cycles.

If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP

(see Figure 12: PLL output frequency timing diagram).

Figure 14. RESET sequence phases

Table 8.

CPU Clock cycle delay

Clock source

CPU clock

cycle delay

Internal RC oscillator

256

External clock (connected to CLKIN pin)

256

External crystal/ceramic oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active phase

Internal reset

256 or 4096 clock cycles

Fetch

vector

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