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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITE20F2 数据表(PDF) 87 Page - STMicroelectronics |
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ST7LITE20F2 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Doc ID 8349 Rev 5 87/166 The LTICR is a read-only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. Timebase counter 2 Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value stored in the LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the LTARR reload value. Software can write a new value at anytime in the LTARR register, this value will be automatically loaded in the counter when the next overflow occurs. When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register. Figure 41. Input capture timing diagram 11.3.4 Low power modes 04h 8-bit COUNTER 1 t 01h fOSC/32 xxh 02h 03h 05h 06h 07h 04h LTIC PIN ICF FLAG LTICR REGISTER CLEARED 4µs (@ 8MHz fOSC) fCPU BY S/W 07h READING LTIC REGISTER Table 37. Effect of low power modes on Lite timer Mode Description SLOW No effect on Lite timer (this peripheral is driven directly by fOSC/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting |
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